Portable electronic devices, such as cellular devices, include processors or compilers, and compiler memory which can include static random access memory or SRAM. Since it is a continuous goal to make electronic devices smaller, it becomes a goal to make SRAM devices smaller. The industry has characterized size for devices such as SRAM as to contact size, particular examples are larger “65 nm” technology, smaller “45 nm” technology, and even smaller “32 nm” technology. It is expected that sizes will further evolve (grow smaller) from “32 nm” technology.
As SRAM devices decrease in size, certain problems are presented. One such problem is the ability to efficiently read from and write to SRAM devices, and particularly reading from and writing to memory or bit cells of SRAM devices. SRAM bit cells are typically arranged in an array (or arrays) with columns and rows of bit cells. As SRAM become smaller, there may be a need to provide read and write assist circuits to make such higher density bit cells work.
Such read and write assist circuits may require charging or discharging of power rails and/or signals such as bit lines, which run in the column dimension. Tight tolerances may be required to support moving and controlling a change in voltage (i.e., delta V) of these power rails and/or bit lines. A particular problem arises as to how a pulse can be generated to move these power rails and/or bit lines a fixed delta V when the capacitance of the bit lines varies as the number of rows of bit cells along the bit line increase or decreases. This is the case when SRAM is used as compiler memory, where the number of word lines which determine bit line length varies. For example, in one application there may be eight word lines that translate to a relatively short bit line, and in another application there may be 256 word lines that translate to a relatively longer bit line length.